1. Field of the Invention
The present invention relates to a high level synthesis device, a method for generating a model for verifying hardware, a method for verifying hardware, a control program, and a readable recording medium. More specifically, the present invention relates to a high level synthesis device for generating a cycle accurate model, for verifying hardware at a cycle accurate level (the precision of a clock cycle), with a general-purpose programming language; a method for generating such a cycle accurate model; a method for verifying hardware using such a cycle accurate model; a control program for causing a computer to execute such a method; and a readable recording medium having such a control program recorded thereon.
2. Description of the Related Art
Recently, in developing large-scale system LSIs, it is verified whether the operation of designed hardware satisfies certain specifications required of a corresponding system or not by simulation.
Conventionally, hardware is verified at a cycle accurate level using an HDL (Hardware Description Language) simulator. It is verified by simulation using the HDL simulator whether a performance of the hardware, such as an operating speed or the like, satisfies specifications required of the system.
Generally an HDL simulator simulates a circuit operation described with a hardware description language such as, for example, VHDL (Very High Speed Integrated Hardware Description Language). The HDL simulator performs a simulation with an event driving system. Namely, the HDL simulator monitors a signal change in the circuit at a time unit which is shorter than a clock cycle, and propagates the signal change in the circuit to a signal which is transmitted through a line connected to the circuit.
In a system including hardware and software, an operation of the hardware described with a hardware description language and an operation of the software described with a general-purpose programming language can be verified in association with each other. In such a case, the hardware is debugged using an HDL simulator, and the software is debugged using a software debugger.
Use of an HDL simulator for performing a simulation with an event driving system to verify hardware has the following problems. The time unit of simulation is shorter than a clock cycle. Accordingly, verification of hardware at a cycle accurate level accompanies redundant and wasteful calculations, which reduces the efficiency. In the case where the circuit to be verified is large-scale or the test pattern is long, the simulation requires a great amount of calculation and is time-consuming. In addition, an HDL simulator is expensive, which increases the cost for developing the system LSI.
As described above, hardware described with a hardware description language and software described with a general-purpose programming language can be verified in association with each other by debugging the hardware by an HDL simulator and debugging the software by a software debugger. In such a case, the debuggers are of different languages. It is time-consuming to match the languages, which reduces the efficiency.
With these problems, methods for verifying hardware without using an HDL simulator have been studied.
Japanese Laid-Open Publication No. 10-149382 discloses a method for verifying hardware and software in association with each other by simulating an operation of the hardware using a general-purpose programming language.
According to this method, hardware devices which operate in parallel are represented by a general-purpose programming language, for example, the C language. Such hardware devices are debugged so as to verify the hardware and software in association with each other. This provides high efficiency. Although this method can verify hardware at an algorithm level, the verification precision at a cycle accurate level is low. Thus, this method cannot verify whether the hardware satisfies certain specifications, including the operating speed, required of the system.
Japanese Laid-Open Publication No. 2001-14356 discloses a method for verifying hardware at a cycle accurate level at high speed. According to this method, an operation description which indicates the operations of all the arithmetic operators of the hardware is generated, and a verification model is generated with a general-purpose programming language.
The verification model disclosed in Japanese Laid-Open Publication No. 2001-14356 can cause a circuit obtained by high level synthesis to operate at a level equivalent to a cycle accurate level. However, this verification model cannot monitor the state of the circuit at an arbitrary clock cycle.